The disclosure relates to an oscillator circuit and a method for generating a clock signal.
Oscillators are one of the basic building blocks of every digital and mixed-signal circuit. In many applications the performance of the circuit is highly dependent on the performance of the oscillator, requiring low frequency drift over the temperature, low jitter and high power supply rejection ratio. In addition, low power consumption is often required. Quartz oscillators offer a great frequency precision. However, their temperature range is usually limited to 125° C. In addition, they are not suitable for the full on-chip solutions, because they require an external component, namely the quartz, which implies high production cost.
A so-called relaxation oscillator is therefore commonly used instead of a quartz oscillator. The present application starts out from a well-known conventional saw-tooth relaxation oscillator which is depicted in FIG. 6. The oscillator has two integrator blocks 10, 20. The integrator block 10 comprises two switches 11, 12, an inverter 13, a capacitor 14, a comparator 15 and a current source 16. The integrator block 20 has two switches 21, 22, an inverter 23, a capacitor 24, a comparator 25 and a current source 26. The integrator blocks 10 and 20 are presumed identical in terms of the composition and all electrical properties. The outputs A and B of the comparators 15 and 25 control an SR flip-flop 30, which provides the signals CLK1 and CLK2 at its outputs. The signals CLK1 and CLK2 control the switches 11 and 12 of the integrator block 10 and switches 21 and 22 of the integrator block 20. It is assumed that the voltage reference VREF and the current reference IREF are provided by means of a reference generator block which is not shown in the schematics.
The operation of the circuit depicted in FIG. 6 is described with reference to FIG. 7, which shows typical waveforms of the voltages of the relevant nodes of the circuit diagram. At the beginning, the output voltages of the SR flip-flop 30, CLK1 and CLK2, are presumed high and low, respectively. The capacitors 14 and 24 are completely discharged. The output voltages A and B of the comparators 15 and 25 are both set to ground. Consequently, switches 11 and 22 are open, while switches 12 and 21 are closed. This ensures that the voltage V1 across the capacitor 14 is held at the ground level, while the capacitor 24 is being charged with the current IREF from the current source 21, linearly increasing the voltage V2 with a slew rate equal to the quotient of the current IREF and the capacitance value C of capacitor 24. At the moment ta, when the voltage V2 reaches the reference voltage VREF, the output current of the comparator 25 starts to charge the parasitic capacitances at its output B. The voltage at output B reaches a threshold voltage VTHR, representing the switching level of comparator 25, after a delay time td. This corresponds to the moment tb. At the moment tb, the reset signal of the SR flip-flop 30 is activated and the state of the flip-flop changes. Consequently, the voltage CLK1 changes its state from high to low, while the voltage CLK2 changes its state from low to high. All switches change their state as a result of change of the control voltages CLK1 and CLK2. The switches 11 and 22 change from open state to closed, while the switches 12 and 21 change from closed state to open. Therefore, the voltage V2 is discharged to the ground level, while the capacitor 14 starts to charge with the current IREF from the current source 16, rendering a slew rate of the voltage V1 equal to the quotient of the current IREF and the capacitance value C of capacitor 14. Because of the complete symmetry of the two integrator blocks 10 and 20, the waveform of the voltage V1 from tb to te is equal to the waveform of the voltage V2 up to tb. Considering this, one complete cycle of the voltages V1 and V2 extends from the beginning to point in time te and is called period T′.
In order to calculate the period T′ of the oscillation for the circuit in FIG. 6, it becomes clear from the waveform of the voltage V2, that the moment to is determined with the slew rate of the voltage V2 and the reference voltage VREF. Furthermore, the propagation delay of the comparator which corresponds to timespan td is added to a half-cycle duration of the relaxation oscillator. The half-cycle duration is then equal to:
                                          T            ′                    2                =                              C            *                          VREF              IREF                                +          td                                    (        1        )            
wherein T′ represents the period or cycle duration, VREF represents the reference voltage VREF, C represents the capacitance value C of the capacitor 14 or 24, IREF represents the current IREF and td represents the propagation delay td of the comparator 15 or 25.
The period is equal to:
                                          T            ′                    2                =                              2            *            C            *                          VREF              IREF                                +                      2            ⁢            td                                              (        2        )            which can also be written as:T′=2RC+2td  (3)
wherein R represents the reference value of the resistor R resulting from the quotient of the reference voltage VREF and the current IREF.
One drawback of the prior art solution shown in FIG. 6 is the influence of the comparator propagation delay td on the absolute value of the oscillation frequency. The propagation delay td adds an additional frequency drift over temperature, power supply and process variations. This impairs the overall precision of the oscillator.
In the prior art e.g. U.S. Pat. No. 8,054,141 B2 said issue of the comparator propagation delay has been addressed. FIG. 8 shows the simplified circuit diagram of a relaxation oscillator 500. The relaxation oscillator 500 includes an integrator 501, a duplicate integrator 502, two reference voltages Vhigh and Vlow, a comparator 503 and logic 504. Integrator 501 has current sources I1 and I2, switches SW1 and SW2 and capacitor Ca. Duplicate integrator 502 includes current sources I3, I4 and I5, switches SW3, SW4, SW5 and SW6 and capacitor Cb.
The operation of the relaxation oscillator depicted in FIG. 8 is based on the integrator 501 and the comparator 503. As the switches SW1 and SW2 operate in tandem, the capacitor Ca either charges or discharges, depending on the state of the logic 504. The comparator output changes the state of the logic 504 after the voltage Vcap reaches one of the reference voltages Vhigh or Vlow with a delay td. Meanwhile, a pulse with the duration of the delay td is extracted from the output of the comparator 503. This pulse controls the operation of the duplicate integrator 502, feeding the capacitor Cb with excess charge in order to cancel the delay of the comparator 302. As a result, the voltage on the capacitors Ca, Cb is shifted by the amount corresponding to the delay.
However, the precision of the delay cancelation shown in FIG. 8 is determined by the exactness of the propagation delay pulse duration, together with the matching of the current sources and the capacitors contained in the integrators 501 and 502. While the matching quality can be controlled and set to a desirable level, the exact extraction of the propagation delay pulse strongly depends on the process corners, symmetrical slew rates and the linear behavior of the comparator circuit. This entails a systematic error in the extraction of the delay pulse.